g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 1 - features : description : * 32k x 8-bit organization. * very high speed ? 8,10,12,15 ns. * low standby power. maximum 2ma for glt7256l08. * fully static operation * 3.3v 5% power supply. * ttl compatible i/o. * three state output. * chip enable for simple memory expansion. * available in 28 pin 300 mil soj and tsop packages. glt7256l08 are high performance 256k bit static random access memories organized as 32k by 8 bits and operate at a single 3.3 volt supply. fabricated with g-link technology's very advanced cmos sub- micron technology, glt7256l08 offer a combination of features: very high speed and very low stand-by current. in addition, this device also supports easy memory expansion with an active low chip enable ( ce ) as well as an active low output enable ( oe ) and three state outputs. pin configurations : function block diagram : glt7256l08
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 2 - pin descriptions: name function a 0 - a 14 address inputs ce chip enable input oe output enable input we write enable input i/o o - i/o 7 data input and data output v cc +3.3v power supply gnd ground truth table: mode we ce oe i/o operation v current cc not selected (power down) x h x high z i ,i ccsb ccsb1 output disabled h l h high z i cc read h l l d out i cc write l l x d in i cc absolute maximum ratings: operation range: range temperature v cc commercial 0 c to + 70 c o o 3.3v 5% ambient temperature under bias ...................................-10 c to +80 c storage temperature(plastic)....-55 c to +125 c voltage relative to gnd.............-0.5v to + 4.6v data output current..................................50ma power dissipation ......................................1.0w sym. p arameter conditions max. unit 1. stresses greater than those listed under absolute maximum rating may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. c in c i/o input capacitance input/output capacitance v in =0v v i/o =0v 8 10 pf pf capacitance ( 1) t a =25 c,f=1.0mhz :
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 3 - dc characteristics sym. parameter test conditions min. typ (1) max. unit v il guaranteed input low voltage (2) -0.3 - +0.8 v v ih guaranteed input high voltage (2) 2.0 - v cc +0.3 v i li input leakage current v cc =max., v in =0v to v cc -5 - 5 m a i lo output leakage current v cc =max., ce 3 v ih -5 - 5 m a v ol output low voltage v cc =min.,i ol =8ma - - 0.4 v v oh output high voltage v cc =min., i oh =-4ma 2.4 - - v i cc operating power supply current v cc =max., ce v il , i i/o =0ma., f=f max (3) - - -8 -10 -12 -15 110 100 90 90 ma i ccsb standby power supply current v cc =max., ce 3 v ih , i i/o =0ma., f=f max (3) - - 15 ma i ccsb1 power down power supply current v cc =max., ce 3 v cc .-0.2v, v in 3 v cc . -0.2v or - - 2 ma 1. typical characteristics are at v cc =3.3v, t a =25 c. 2. these are absolute values with repeat to device ground and all overshoots due to system or tester noise are included. 3. f max =1/t rc . data retention (l version only) sym. parameter test conditions min. typ (1) max. unit v d r v cc for data retention ce 3 v cc -0.2v, v in 3 v cc -0.2v or v in 0.2v 2.0 - 3.6 v i ccdr (1) data retention current v dr =2.0v 30 m a t cdr chip deselect to data retention time retention waveform 0 - - ns t r operating recovery time t rc (2) - - ns 1. ce 3 v dr -0.2v, v in 3 v dr -0.2v or v in 0.2v. 2. t rc =read cycle time.
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 4 - low v cc data retention waveform (ce controlled) ac test conditions input pulse levels 0v to 3.0v input rise and fall times timing reference level 3 ns 1.5v ac test loads and waveforms w w w w w ac electrical characteristics (over the commercial operating range) read cycle -8 -10 -12 -15 parameter name parameter min max min max min max min max unit t rc read cycle time 8 10 12 15 ns t aa address access time 8 10 12 15 ns t acs chip select access time, 8 10 12 15 ns t oe output enable to output valid 5 6 7 8 ns t clz chip select to output low z, ce 3 3 3 3 ns t olz output enable to output in low z 0 0 0 0 ns t chz chip deselect to output in high z, ce 4 0 5 0 6 0 6 ns t ohz output disable to output in high z 4 0 5 0 6 0 6 ns t oh output hold from address change 3 3 3 3 ns
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 5 - switching waveform (read cycle) read cycle1 (1,2,4) read cycle 2 (1,3,4) read cycl e 3 (1) notes: 1. we is high for read cycle. 2. device is continuously selected ce v il . 3. address valid prior to or coincident with ce transition low and/or transition high. 4. oe v il . 5. transition is measured 200mv from steady state with c l =5pf.
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 6 - ac electrical characteristics (over the commercial operating range) write cycle -8 -10 -12 -15 parameter name parameter min max min max min max min max unit t wc write cycle time 8 10 12 15 ns t cw chip select to end of write 6 8 10 12 ns t a s address set up time 0 0 0 0 ns t aw address valid to end of write 6 8 10 12 ns t wp write pulse width 6 8 10 12 t wr write recovery time 0 0 0 0 ns t whz write to output in high z 0 4 0 5 0 6 0 ns t dw data to write time overlap 5 6 8 10 6 ns t dh data hold from write time 0 0 0 0 ns t ow end of write to output active 0 0 0 0 ns switching waveforms(write cycle) write cycle 1 (1)
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 7 - switching waveform (write cycle) write cycle 2 (1,6) note: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap ce low and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, i/o pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, outputs remain in a high impedance state. 6. oe is continuously low ( oe =v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. transition is measured 200mv from steady state with c l =5pf. 11. t cw is measured from ce going low to the end of write.
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 8 - ordering informstion part number cycle time power package glt7256l08-8 j3 8 ns low power soj 300mil 28l GLT7256L08-10J3 10ns low power soj 300mil 28l glt7256l08-12j3 12ns low power soj 300mil 28l glt7256l08-15j3 15ns low power soj 300mil 28l glt7256l08-8 ts 8 ns low power tsop glt7256l08-10ts 10ns low power tsop glt7256l08-12ts 12ns low power tsop glt7256l08-15ts 15ns low power tsop parts numbers (top mark) definition : glt 7 256 l 08 - 10 j3 note : c cdrom , h hdd. example : 1.glt710008- 15t 1mbit(128kx8)15ns 5v sram pdip(300mil)package type. 2.glt44016- 40j4 4mbit(256kx16)40ns 5v dram soj(400mil)package type. 4 : dram 6 : standard sram 7 : cache sram 8 : synchronous burst sram -sram 064 : 8k 256 : 256k 512 : 512k 100 : 1m -dram 10 : 1m(c/edo)* 11 : 1m(c/fpm)* 12 : 1m(h/edo)* 13 : 1m(h/fpm)* 20 : 2m(edo) 21 : 2m(fpm) 40 : 4m(edo) 41 : 4m(fpm) 80 : 8m(edo) 81 : 8m(fpm) *see note voltage blank : 5v l : 3.3v m : mix voltage config. 04 : x04 08 : x08 16 : x16 32 : x32 speed -sram 10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -dram 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns package t : pdip(300mil) ts : tsop(type i) tc : tsop(type ll) pl : plcc fa : 300mil sop fb : 330mil sop fc : 445mil sop j3 : 300mil soj j4 : 400mil soj p : pdip(600mil) q : pqfp tq : tqfp
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 9 - package information 300mil 28 pin small outline j-form package (soj)
g-link glt7256l08 ultra high performance 3.3v 32k x 8 bit cmos static ram mar 2000(rev. 2.0) g-link technology corporation 2701 northwestern parkway santa clara, ca 95051, u.s.a. g-link technology corporation ,taiwan 2f, no.12, r&d rd. ii, science-based industrial park, hsin chu, taiwan, r.o.c. - 10 - tsop 28 pin plastic dual inline package
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